Although during the Fifties and Sixties magnetic core memories were the predominant storage technology for the working memory of computing systems, they were rapidly supplanted during the Seventies by the integrated circuit random access memory, both static (SRAM) and dynamic (DRAM). The advantages of these newer technologies are well known: microscopic size (contributing to higher operating speeds), miniscule power requirements (requiring dissipation of less waste heat), improved robustness and thus reliability, and manufacturing efficiencies of scale--all of which contributed to the dramatically reduced cost per bit. The disadvantages are equally well known: data volatility, reflected as continuous power dissipation in SRAMs, and as periodic data refresh in DRAMs. To address these problems, various types of non-volatile, read/write memory technologies have been developed, including electrically erasable programmable read only memory (EEPROM), of which Flash memory is, at present, the most popular. All such technologies, however, have additional disadvantages, including finite lifetimes (in terms of write cycles), and power supply requirements which challenge designers of battery powered systems.
Recently, magnetoresistive random access memory (MRAM) cells suitable for fabrication using current integrated circuit manufacturing processes have been developed for use as non-volatile storage elements. Examples of such an MRAM cell suitable for implementation in an IC are shown and described in U.S. Pat. Nos. 5,343,422, 5,917,749, and 5,920,500. A survey of current MRAM technologies and their relative advantages and disadvantages was published by R. Scheuerlein in "Magneto Resistive IC Memory Limitations and Architecture Implications", 1998 International Non-Volatile Memory Technology Conference, IEEE, pp. 47-50 (1998).
In general, MRAM devices of the Magnetic Tunnel Junction (MTJ) type include a multi-layer resistor element comprised of suitable magnetic materials which change its resistance to the flow of electrical current depending upon the direction of magnetic polarization of the layers. In a memory cell, this "bit.sub.-- resistor" is connected in series with a "bit.sub.-- read" transistor between a common voltage supply and a "bit.sub.-- read.sub.-- write" conductor connected to an input of a "read" sense amplifier. A "word.sub.-- write" conductor is arranged to intersect, relatively orthogonally, the bit.sub.-- read.sub.-- write conductor. The word.sub.-- write and the bit.sub.-- read.sub.-- write conductors are connected to respective word.sub.-- write and bit.sub.-- write driver circuits which are selectively enabled such that each conductor conducts only a portion of the current necessary to switch the polarization state of the bit resistor.
During a write operation, each of these "write" currents is generally insufficient to affect the polarization state of any bit.sub.-- resistor, but, together, at the point of intersection or "coincidence", the currents are sufficient to affect the polarization state of that bit.sub.-- resistor which is proximate to the intersection of the write conductors. Depending upon the present state of polarization and the relative directions of current flow in the write conductors, the bit.sub.-- resistor at the coincidence point will either maintain or switch its polarization state.
During a read operation, the bit.sub.-- read transistor is enabled via a respective word.sub.-- read conductor, and, simultaneously, the corresponding bit.sub.-- read sense amplifier is enabled to create a current path from the bit.sub.-- read.sub.-- write conductor to the common supply. Since the difference in the resistance value of the bit.sub.-- resistor is small, the bit.sub.-- read sense amp must be sufficiently sensitive to recognize the small differences in voltage drop across the bit.sub.-- resistor associated with the respective polarization states. As was the case with magnetic core memories, an MRAM bit.sub.-- resistor, once written, will retain its magnetic polarization state indefinitely, with no further input of power. Similarly, there appears to be no practical limit on the number of times that the polarization of the bit.sub.-- resistor itself can be switched or "written".
One of the unfortunate characteristics of such MRAM cells is the relatively large write currents required to switch the magnetic polarization of the bit.sub.-- resistor. As improvements in process technologies decrease the cross-sectional area of the write conductors, metal migration effects become significant. Corresponding improvements are needed to reduce the levels of the write currents or the frequency of their application to the MRAM cells.
In U.S. Pat. No. 5,777,923, a method is disclosed for comparing, on a bit-wise basis, the logic state of a data bit stored in a Flash memory cell and the logic state of a respective input bit, and to inhibit that cell during back-to-back erase and program cycles. A principle objective of this method is to prolong the lifetime of each Flash cell by eliminating unnecessary erase and program operations. However, the disclosed method and implementation are not directly applicable to an MRAM system, primarily because of the significantly different techniques for writing the two types of cells.
It is an object of the present invention to provide a method for detecting, on a bit-wise basis, a correspondence between the logic state of a data bit stored in an MRAM cell and the logic state of a respective input bit, and to disable the bit.sub.-- write driver circuit during a write cycle, thus conserving the bit.sub.-- write current.
The rapid reduction in structure geometries also increases the likelihood that, in the course of writing a particular MRAM cell, or set of cells, other cells in the array may be inadvertently switched. This is even more likely in the context of one embodiment of the present invention in which one of the pair of write currents to a cell (corresponding to a particular "bit" of a selected multi-bit "word") is disabled because the state of the cell is already correct. Although external error detection and correction (EDAC) technologies may be employed to detect and correct such data corruption, such technologies have well-known limits, and significantly increase system cost, power consumption, etc.
A further object of the present invention is to provide a method for reinforcing, during a write operation, the polarization state of MRAM cells which are not to be changed, thus protecting vulnerable cells.
In a conventional precharge/discharge memory, such as a read-only memory (ROM), a technique has been developed to minimize, on the average, the number of precharged bit lines that are discharged in the course of accessing each multi-bit row. According to this technique, shown and described in U.S. Pat. No. 5,896,335 (which is assigned to the present Assignee, and hereby expressly incorporated herein by reference), the logical state of each bit comprising a word is inverted if, by doing so, the number of precharged bit lines that will be discharged during a read of the row will be minimized. In order to keep track of this selective row-wise bit inversion, a reversion bit is added to each row, and set or reset accordingly. The resulting savings in power dissipation can be quite significant, especially in large memories.
Another object of the present invention is to provide a method, for use in an MRAM system, to minimize, on the average, the number of cells comprising a multi-bit word which must be simultaneously programmed, thus minimizing both the instantaneous, peak and average current draw of the memory.
In addition, the present invention is directed to suitable apparatus for practicing each of the methods disclosed hereinafter.